Yu Wang's Homepage

News

• (2014/04/30) We initialize our new group Website: http://nicsefc.ee.tsinghua.edu.cn/
• (2011/07/20) We release our parallel sparse linear solver: NICS-LU at [nicslu.weebly.com], which is capable to solve very large scale sparse matrix decomposition on shared memory multicores (we tested on 12 cores). It can be easily integrated into your own software for parallel LU decomposition. Try it!!
• (2012/08) Dr. Hong Luo's paper "Temporal Performance Degradation under RTN: Evaluation and Mitigation for Nanoscale Circuits" , won the Best Paper Award in ISVLSI 2012 ( IEEE Computer Society Annual Symposium on VLSI ), Co-authors: Yu Wang, Yu Cao, Yuan Xie, Yuchun Ma and Huazhong Yang.
• (2012/05) Yi Shan's paper (joint work with Prof. Wayne Luk's group), "FPGA based Stereo Vision System for Future Video Tolling" , won the Best Poster Award in HEART 2012 (International Workshop on Highly-Efficient Accelerators and Reconfigurable Technologies).
• (2012/05) Xiaoming Chen who is supervised by Prof. Huazhong Yang and Yu Wang won the Student Travel Award in IPDPS 2012
• (2012/03) Yi Shan who is supervised by Prof. Xu Chen, Huazhong Yang and Yu Wang got the IBM Phd Fellowship Award.
• (2012/01) Xiaoming Chen who is supervised by Prof. Huazhong Yang and Yu Wang got the Best Paper Nomination in ASPDAC 2012.
• (2012/05/25) Dr. Yiyu Shi, Assistant Professor, Electrical and Computer Engineering Department at Missouri University of Science and Technology (formerly University of Missouri, Rolla) visited our lab and gave a talk on "TSV-Oriented Three-dimensional Integrated Circuit Design: the Good, the Bad, and the Amazing Grace".
• (2012/05/17) Xinyu Niu, Phd Candidate in Prof. Wayne Luk's group, Imperial College London visited our lab and gave a talk on "Self-adaptive Heterogeneous Computing".
• (2012/01/05) Andrew Kegel, Gabriel Loh, Principle Researcher of AMD visited our lab and gave two talks on "The AMD Global Research Initiative" and "Challenges and Opportunities with Die-Stacked DRAM in High-Performance Computer Architectures".
• (2011/08/11) Dr. Onur Mutlu, Assistant Prof. in CMU, visitied our lab and gave a talk on "Memory Systems in the Many-Core Era: Challenges, Opportunities, and Solution Directions".
  
• (2011/7/22) Dr. Ray Cheung, Assistant Prof. in City U, HK, visited our lab and gave a talk on "CALAS: High Speed Pairing Coprocessor Using RNS Multiplier".
• (2011/6/30) Dr. Zhijie Shi, Associate Professor in the Department of Computer Science and Engineering at the University of Connecticut visited our lab and gave a talk on "Recent work on the development of underwater acoustic modem".
• (2011/06/21) Dr. Qiang Xu, Assistant Prof., Department of Computer Science & Engineering, The Chinese University of Hong Kong visited our lab and gave a talk on "Variation-Induced Timing Uncertainty - A Design and Test Perspective".
• (2011/06/02) Prof. Yinhe Han (ICT, China) visited our lab and gave a talk on "可重构片上网络体系结构研究".
• (2011/03/04) Dr. Jin Ouyang (PSU, USA) visited our lab and gave a talk on "Optical NoC: Future Replacement for On-Chip Interconnects".
• (2011/02/14) Dr. Bin Li, research scientist in Intel Labs visited our lab and gave a talk on "A Template-based Memory Access Engine Design for Accelerator Centric SoC Platforms".
• (2010/10/31) We got the Second prize of AMD GPU competition, China, 2010. (Our Team: BrainStrom Tsinghua, Team member: Di Wu, Yi Shan, Xiaorui Zhang, Yu Wang) NEWS
• (2010/11/12) Prof. Lei He (University of California, Los Angeles) visited our lab and gave a talk on "Reliable Circuits and Systems for Internet and New Energy".
• (2010/11/08) Dr. Meng-Fan Chang，Assistant Prof. National Tsing Hua University, Taiwan visited our lab and gave a talk on "Embedded Memory Circuit Design Challenges and Trends for Mobile SoC and 3D-IC".
• (2010/08/20) 招生：电路与系统研究所招博士生和硕士生，课题主要和国外高校和国内外知名企业合作，有较多实习和交流机会，以文章发表和系统实现为毕业条件。踏实、勤奋，对C/C++编程以及FPGA开发较熟的同学优先。目前主要项目包括，标注出主要合作方：针对低功耗多核系统的片上传感网设计（香港科技大学、KTH）；基于FPGA/GPU的机器学习算法研究（微软、AMD、IBM、云加速）；低功耗、高可靠性三维多核系统设计方法学（PSU、ASU、HKUST）；并行电路仿真（UCSD、华大、NTU）。
• (2010/08/09) Dr. Qiang Liu from Imperial College Custom Computing Research Group visited our lab
• (2010/07/29) Prof. Hao Yu from NTU visited our lab
• (2010/07/19) Dr. Zhonghai Lu from KTH visited our lab
• (2010/06/29) Prof. Jiang Xu from HKUST visited our lab
• (2010/02) Two new projects on Brain Network computing and Video computing lauched in 2010, supported by MSRA and MHI respectively.
• (2010/01) Two papers nominated as Best Paper Candidate in ASPDAC 2010.
• (2009/11) Best Paper Nomination in CODES 2009.
• (2009/10/31) We got the first prize of AMD GPU competition, China, 2009. (Our Team: Sokudo Tsinghua, Team member: Tianji Wu, Bo Wang, Feng Yan, Yu Wang) NEWS
• (2009/08/19) Best Paper Nomination in ISLPED 2009, 7 of 72. (Xiaoming Chen, Yu Wang, Yu Cao, Yuchun Ma, Huazhong Yang, "Variation-Aware Supply Voltage Assignment for Minimizing Circuit Degradation and Leakage") NEWS
• (2009/03/20) Dr. Wenzhuo Liu from AMD China visited Tsinghua, hosted by E.E. Dept.
• (2008/11/11) “Multi-Metric Incremental Floorplanning for SOC” is granted by TNLIST (Tsinghua National Laboratory for Information Science and Technology) , Co-PI. (PI: Dr. Yuchun Ma)
• (2008/10/26 - 2009/01/30) Visting HKUST, hosted by Prof. Jiang XU
• (2008/09/05) "Research on FPGA based Anti-Degradation Machine Learning " is granted by NSF China from 2009 to 2011, PI.
• (2008/06/25) Prof. Chris H Kim from MNU visited our lab
• (2008/05/19) Prof. David Blaauw from U. Mich. visited our lab
• (2008/04/28) Prof. Jiang Xu from HKUST visited our lab
• (2008/04/17) Dr. Feng-Hsiung Hsu from MSRA visited our lab
• (2008/04/01) "FPGA based accelerator for Machine Learning" is granted by MSRA

DBLP Link: 汪玉, EE Dept. Tsinghua University, Beijing, China

Seleted Journal Publications

• [IEEE TCAS II] Xiaoming Chen*, Wei Wu*, Yu Wang, Hao Yu, Huazhong Yang, "An EScheduler based Data Dependency Analysis and Task Scheduling for Parallel Circuit Simulation", to appear in IEEE Trans on Circuits and Systems II. [PDF & software download from nicslu.weebly.com]
• [IEEE TDSC] Yu Wang, Hong Luo, Ku He, Rong Luo, Huazhong Yang, Yuan Xie, "Temperature-Aware NBTI Modeling and the Impact of Standby Leakage Reduction Techniques on Circuit Performance Degradation", to appear in IEEE Trans on Dependable and Security Computing.
• [IEEE TVLSI] Yu Wang , Ku He, Rong Luo, Hui Wang, Huazhong Yang, “Two-phase Fine-grain Sleep Transistor Insertion Technique in Leakage Critical Circuits,” in IEEE Transaction on VLSI, Volume 16, Issue 9, Sept. 2008 Page(s):1101 - 1113. [PDF]
• [IEEE TVLSI] Yu Wang, Xiaoming Chen, Wenping Wang, Yu Cao, Yuan Xie, Huazhong Yang, "Leakage Power and Circuit Aging Co-Optimization by Gate Replacement Techniques", to appear in TVLSI.
• [IEEE TVLSI] Yu Wang, Jiang Xu, Yan Xu, Weichen Liu, Huazhong Yang, " Power Gating Aware Task Scheduling in MPSoC", to appear in IEEE Trans on VLSI.

Selected Conference Publications

• [ASQED] (invited paper) Yu Wang, Yong He, Yi Shan, Tianji Wu, Di Wu and Huazhong Yang, "Hardware Computing for Brain Network Analysis", in ASQED 2010.
• [CASES] Yu Wang, Jiang Xu, Shengxi Huang, Weichen Liu, Huazhong Yang, "A Case Study of On-Chip Sensor Network in Multiprocessor System-on-Chip", in CASES 2009.
• [ISLPED2009] Xiaoming Chen, Yu Wang, Yu Cao, Yuchun Ma, Huazhong Yang, "Variation-Aware Supply Voltage Assignment for Minimizing Circuit Degradation and Leakage", in ISLPED 2009.
• [ISQED2009] Yu Wang, Xiaoming Chen, Wenping Wang, Varsha Balakrishnan, Yu Cao, Yuan Xie, and Huazhong Yang, "On the efficacy of Input Vector Control to mitigate NBTI effects and leakage power", in ISQED2009.
• [DATE2009] Yu Wang, Xiaoming Chen, Wenping Wang, Yu Cao, Yuan Xie, Huazhong Yang, "Gate Replacement Techniques for Simultaneous Leakage and Aging Optimization", in DATE 2009.
• [ASPDAC09] Michael DeBole, Ramakrishnan Krishnan, Varsha Balakrishnan, Wenping Wang, Luo Hong, Yu Wang, Yuan Xie , Yu Cao, N. Vijaykrishnan, " A Framework for Estimating NBTI Degradation of Microarchitectural Components", in ASPDAC 2009.
• [APCCAS08] Yu Wang, Kai Zhou, Zhonghai Lu, Huazhong Yang, "Dynamic TDM Virtual Circuit Implementation for NoCs", in APCCAS 2008.
• [ISQED08] Qian Ding, Yu Wang, Hui Wang, Rong Luo, Huazhong Yang, " Output Remapping Technique for Soft-Error Rate Reduction in Critical Path, " in ISQED08, pp. 74-77 .
• [ASPDAC08] Saihua Lin, Yu Wang, Rong Luo, Huazhong Yang, "A Capacitive Boosted Buffer Technique for High-Speed Process-Variation-Tolerant Interconnect in UDVS application ," in ASPDAC2008, pp. 304-309.
• [PATMOS07] Hong Luo, Yu Wang , Ku He, Rong Luo, Huazhong Yang, Yuan Xie, “A Novel Gate-level NBTI Delay Degradation Model with Stacking Effect,” in PATMOS07, pp. 160-170.
• [ISQED07] Hong Luo, Yu Wang , Ku He, Rong Luo, Huazhong Yang, Yuan Xie, “Modeling of PMOS NBTI Effect Considering Temperature variation,” in ISQED07, pp. 139-144.
• [DATE07] Yu Wang , Hong Luo, Ku He, Rong Luo, Huazhong Yang, Yuan Xie, “NBTI Modeling and Impact on the Input Vector Control Technique Considering Temperature Variation,” in DATE 2007, pp. 546-551.
• [ISLPED06] Yu Wang , Yongpan Liu, Rong Luo, Huazhong Yang, Hui Wang, "Two-phase Fine-grain Sleep Transistor Insertion Technique in Leakage Critical Circuits," in Proc. of ISLPED06, pp:238-243.
• [PATMOS06] Hai Lin, Yu Wang , Huazhong Yang, Rong Luo, Hui Wang, “IR-drop Reduction through Combinational Circuit Partitioning,” in Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation (PATMOS 2006), LNCS 4148, pp. 370–381, 2006.
• [ISQED06] Yu Wang , Hai Lin, Huazhong Yang, Rong Luo, Hui Wang, “Simultaneous Fine-grain Sleep Transistor Placement and Sizing for Leakage Optimization,” in Proc.of ISQED'06, San Jose, USA, March 2006, pp:723-728.

Presentations

• ASQED'10, Penang, Malaysia, August, "Hardware Computing for Brain Network Analysis".
• Visiting NUS, SG, August, "Recent MPSoC research work in NICS Tsinghua".
• Visiting PSU, USA, April, "Recent MPSoC research work in NICS Tsinghua".
• ASPDAC'10, Taiwan, China, Jan, "Three Dimensional Integrated Circuit (3D IC) Floorplan and Power/Ground Network Co-synthesis".
• ISLPED'09, SF, USA, August, "Variation-Aware Supply Voltage Assignment for Minimizing Circuit Degradation and Leakage".
• DATE'09, Nice, France, April, "Gate Replacement Techniques for Simultaneous Leakage and Aging Optimization".
• APCCAS'08, Macao, China, Dec.,2008, "Dynamic TDM Virtual Circuit Implementation for NoCs".
• ASPDAC'08, Seoul, Korea, January, 2008, “A Capacitive Boosted Buffer Technique for High-Speed Process-Variation-Tolerant Interconnect in UDVS application”.
• ASICON'07, Guilin, China, October, 2007, “Leakage power reduction through dual Vth assignment considering threshold voltage variation”.
• DATE'07, Nice, France , April, 2007, “NBTI Modeling and Impact on the Input Vector Control Technique Considering Temperature Variation ”.
• APCCAS'06, Singapore , December, 2006, “Leakage Optimized DECAP Design for FPGAs”.
• APCCAS'06, Singapore , December, 2006, “Fine-grain Sleep Transistor Placement Considering Leakage Feedback Gate”.
• ISLPED'06, Munich , Germany , October, 2006, “ Two-phase Fine-grain Sleep Transistor Insertion Technique in Leakage Critical Circuits ”.
• PATMOS'06, Montpellier, France, September 2006, “IR-drop Reduction through Combinational Circuit Partitioning”.
• ISQED'06, San Jose , USA , March 2006, “ Simultaneous Fine-grain Sleep Transistor Placement and Sizing for Leakage Optimization”.