Yu Wang's Homepage

Most of the papers are copyrighted by ACM or IEEE or Springer. They are posted here for your personal use, to ensure timely dissemination of research work with no commercial purpose. You can find more papers here: http://nicsefc.ee.tsinghua.edu.cn/

DBLP Link: 汪玉, EE Dept. Tsinghua University, Beijing, China

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ResearcherID Yu Wang

Journal Publications

• [IEEE TCSVT] Wenqiang Wang*, Jing Yan, Ningyi Xu, Yu Wang, Feng-Hsiung Hsu “Real-time High-quality Stereo Vision System in FPGA”, in IEEE Trans on Circuits and Systems for Video Technology.
• [OE] Hong Zhang*, Xue Feng, Boxun Li*, Yu Wang, Kaiyu Cui, Fang Liu, Weibei Dou, and Yidong Huang, “Integrated photonic reservoir computing based on hierarchical time-multiplexing structure”, in Optical Express.
• [IEEE TVLSI] Wulong Liu*, Yu Wang, Guoqing Chen, Yuchun Ma, Yuan Xie, Huazhong Yang, ?“Whitespace-Aware TSV Arrangement in 3-D Clock Tree Synthesis”, accepted by IEEE Transaction on VLSI.
• [IEEE TVLSI] Yu Wang, Song Yao*, Shuai Tao*, Xiaoming Chen*, Yuchun Ma, Yiyu Shi, Huazhong Yang, “HS3DPG: Hierarchical Simulation for 3D P/G Network”, accepted by IEEE Transaction on VLSI.
• [IEEE TCAD] Wujie Wen*, Yaojun Zhang*, Yiran Chen, Yu Wang, Yuan Xie, “PS3-RAM: A Fast Portable and Scalable Statistical STT-RAM Reliability/Energy Analysis Method”, accepted by IEEE Trans on CAD.
• [IEEE D&T] Wulong Liu*, Yu Wang*, Yu Wang, Xue Feng, Yuan Xie, Yidong Huang, Huazhong Yang, “Exploration of Electrical and Novel Optical Chip-to-Chip Interconnects”, accepted by IEEE Design & Test.
• [IEEE TPDS] Xiaoming Chen*, Ling Ren*, Yu Wang, Huazhong Yang, "GPU-Accelerated Sparse LU Factorization for Circuit Simulation with Performance Modeling", accepted by IEEE Trans on Parallel and Distributed Computing.
• [ACM TECS] Yi Shan*, Yuchen Hao*, Wenqiang Wang*, Yu Wang, Wayne Luk, Xu Chen, Huazhong Yang, “Hardware Acceleration for Accurate Stereo Vision System using Mini-Census Adaptive Support Region”, accepted by ACM Trans. on Embedded Computing Systems. [PDF download]
• [ACM JETC] Wulong Liu*, Yu Wang, Yuchun Ma, Yuan Xie, Huazhong Yang, "On-Chip Hybrid Power Supply System for Wireless Sensor Nodes", accepted by ACM J. Emerg. Technol. Comput. Syst. (JETC).
• [IEEE D&T] Xiaoming Chen*, Yu Wang, Yu Cao, Yuan Xie, Huazhong Yang, "Assessment of Circuit Optimization Techniques under NBTI", accepted by IEEE Design & Test of Computers, Special Issue on Variability and Aging.
• [PLOS ONE] Yu Wang , Haixiao Du, Mingrui Xia, Ling Ren, Mo Xu, Teng Xie, Gaolang Gong, Ningyi Xu, Huazhong Yang, Yong He. (2013) A Hybrid CPU-GPU Accelerated Framework for Fast Mapping of High-Resolution Human Brain Connectome. PLoS ONE 8(5): e62789. doi:10.1371/journal.pone.0062789
• [IET-CDS] Xiaoming Chen*, Hong Luo, Yu Wang, Yu Cao, Yuan Xie, Yuchun Ma, Huazhong Yang, "Evaluation and Mitigation of Performance Degradation under RTN for Digital Circuits ", accepted by IET Circuits, Devices and Systems.
• [IEEE TCAD] Xiaoming Chen*, Yu Wang, Huazhong Yang, "NICSLU: An Adaptive Sparse Matrix Solver for Parallel Circuit Simulation", accepted by IEEE Trans. on CAD.
• [IEEE TPDS] Weichen Liu*, Yu Wang, Xuan Wang, Jiang Xu, Huazhong Yang, "On-Chip Sensor Network for Efficient Management of Power Gating Induced Power/Ground Noise in Multiprocessor System-on-Chip", in IEEE Trans. on Parallel and Distributed Systems.
• [AICSP] Bo Zhao, Guangming Yu, Yong Lian, Yu Wang, Huazhong Yang, "A 1.9 GHz ADPLL with 130 reference cycles settling time in 0.18 μm CMOS technology", in Analog Integrated Circuits and Signal Processing, pp 1-9, 2013.
• [IEEE TVLSI] Xiaoming Chen*, Yu Wang, Yu Cao, Yuchun Ma, Huazhong Yang, "Variation-Aware Supply Voltage Assignment for Simultaneous Leakage and Aging Optimization", in IEEE TVLSI.
• [IEEE TCAS II] Xiaoming Chen*, Wei Wu*, Yu Wang, Hao Yu, Huazhong Yang, "An EScheduler based Data Dependency Analysis and Task Scheduling for Parallel Circuit Simulation", in IEEE Trans. on Circuits and Systems II 58 (10): 702~706, 2011. [PDF & software download from nicslu.weebly.com]
• [IEEE TDSC] Yu Wang, Hong Luo*, Ku He*, Rong Luo, Huazhong Yang, Yuan Xie, "Temperature-Aware NBTI Modeling and the Impact of Standby Leakage Reduction Techniques on Circuit Performance Degradation", IEEE Trans. Dependable Sec. Comput. 8 (5): 756~769, 2011. [PDF]
• [IEEE TVLSI] Yu Wang , Ku He*, Rong Luo, Hui Wang, Huazhong Yang, “Two-phase Fine-grain Sleep Transistor Insertion Technique in Leakage Critical Circuits,” in IEEE Transaction on VLSI, Volume 16, Issue 9, Sept. 2008 Page(s):1101 - 1113. [PDF]
• [IEEE TVLSI] Yu Wang, Xiaoming Chen*, Wenping Wang, Yu Cao, Yuan Xie, Huazhong Yang, "Leakage Power and Circuit Aging Co-Optimization by Gate Replacement Techniques", in IEEE Transaction on VLSI, Vol.19, No.4, pp.615-628, April 2011. [PDF]
• [IEEE TVLSI] Yu Wang, Jiang Xu, Yan Xu*, Weichen Liu, Huazhong Yang, " Power Gating Aware Task Scheduling in MPSoC", IEEE Trans. VLSI Syst. 19 (10): 1801~1812, 2011. [PDF]
• [ACM TRETS] Jing Yan*, Ningyi Xu, Xiongfei Cai, Rui Gao, Yu Wang, Rong Luo, Fenghsiung Hsu, "An FPGA-based Accelerator for the Relevance Ranking in Web Search Engines", in ACM Trans on RETS 4 (3): 1~25, 2011.
• [IET CDT] Qian Ding*, Yu Wang , Hui Wang, Rong Luo, Huazhong Yang, Output Remapping Technique for Critical Paths Soft-Error Rate Reduction, IET Computers and Digital Techniques, vol. 4, no. 4, pp. 325 - 333, 2010. [PDF]
• [IET CDS] Guangming Yu*, Yu Wang, Huazhong Yang, Hui Wang, "Fast-Locking All-Digital Phase-Locked Loop with Digitally Controlled Oscillator Tuning Word Estimating and Presetting", IET Circuits, Devices and Systems, vol. 4, no. 3, pp. 207 - 217, 2010. [PDF]
• [IEICE] Hong Luo, Yu Wang, Rong Luo, Huazhong Yang and Yuan Xie," Temperature-aware NBTI Modeling Techniques in Digital Circuits ", in IEICE Trans. on Electronics, E92C(6), pp 875-886, 2009/6.
• [IEICE] Yuchun Ma, Xin Li, Yu Wang, Xianlong Hong, "Thermal-Aware Incremental Floorplanning for 3D ICs based on MILP Formulation", in IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E92A (12): 2979-2989 DEC 2009.
• [IEICE] Kan Wang*, Sheqin Dong, Yuchun Ma, Yu Wang, Xianlong Hong, Jason Cong: Leakage-Aware TSV-Planning with Power-Temperature-Delay Dependence in 3D ICs. IEICE Transactions 94-A(12): 2490-2498 (2011).
• [JCSC] Yu Wang ,Huazhong Yang, Hui Wang, “Signal-path Level Dual-Vt Assignment for Leakage Power Reduction,” [pdf] in Journal of Circuits, System and Computers, 2006, Vol. 15, No. 2, pp:179-216.
• [JCSC] Yu Wang, Xukai Shen, Rong Luo, Huazhong Yang, Leakage power reduction through Dual Vth assignment considering threshold voltage variation,Journal of Circuits, Systems and Computers, vol. 18, no. 7, pp. 1243 - 1261, 2009.
• [IJE] Qian Ding*, Yu Wang, Hui Wang, Rong Luo, Huazhong Yang, SERSim: a Soft Error Rate Simulator and a Case Study for a 32-bit OpenRisc 1200 Microprocessor, International Journal of Electronics, vol. 97, no. 4, pp. 441 - 455, 2010..
• [Springer IJPP] Michael DeBole*, Ramakrishnan Krishnan, Varsha Balakrishnan, Wenping Wang, Luo Hong*, Yu Wang, Yuan Xie , Yu Cao, N. Vijaykrishnan, " NewAge: A Framework for Estimating NBTI Degradation of Microarchitectural Components", in International Journal of Parallel Programming, Volume 37, Number 4, 2009.08, pp 417-431.
• [CJE] Yu Wang , Hong Luo*, Ku He*, Rong Luo, Huazhong Yang, Yuan Xie, “NBTI-aware Dual Vth Assignment for Leakage Reduction and Lifetime Assurance,” Chinese Journal of Electronics, vol. 18, no. 2, pp. 225 - 230, 2009.
• [CJS] Huazhong Yang, Yu Wang , Hai Lin, Rong Luo, Hui Wang, “Fine-grain Sleep Transistor Insertion for Leakage Reduction,” in Chinese Journal of Semiconductors, 2006, Vol.27, No.2, pp:258-265.
• [JECE] Yibo Chen*, Yu Wang, Yuan Xie, Andres Takach, "Parametric Yield Driven Resource Binding in High-Level Synthesis with Multi-Vth/Vdd Library and Device Sizing", to appear in Journal of Electrical and Computer Engineering.
• [JEC] Hong Luo*, Yu Wang, Rong Luo, Huazhong Yang, "Software Tools for Analyzing NBTI-induced Digital Circuit Degradation," in Journal of Electronics (China), Volume 26, Number 5, 2009.09, pp.715-719. .
• [JEST] Bo Zhao*, Yu Wang, Huazhong Yang, and Hui Wang, "The NBTI Impact on RF Front End in Wireless Sensor Networks", in Journal of Electronic Science and Technology 2009 7(4).
• [JoS] Qian Ding*, Yu Wang , Hui Wang, Rong Luo, Huazhong Yang, Soft Error Generation Analysis in Combinational Logic Circuits, to appear in Journal of Semiconductors.
• 史圣卿，陈凯，汪玉，罗嵘. 基于FPGA的稀疏网络关键节点计算的硬件加速方法研究. 电子与信息学报, 2011,V33(10): 2536-2540。(in Chinese)
  

Conference Publications

• 2015
  • [GLSVLSI] Yu Wang, Tianqi Tang, Lixue Xia, Boxun Li, Peng Gu, Hai Li, Yuan Xie, Huazhong Yang, “Energy Efficient RRAM Spiking Neural Network for Real Time Classification”, in GLSVLSI 2015. (invited paper)
  • [DAC] Boxun Li*, Lixue Xia*, Peng Gu*, Yu Wang, and Huazhong Yang. Merging the interface: Power, area and accuracy co-optimization for RRAM crossbar-based mixed-signal computing system. In DAC, 2015.
  • [DAC] Gushu Li*, Xiaoming Chen*, Guangyu Sun, Hank Hoffmann, Yongpan Liu, Yu Wang, and Huazhong Yang. A STT-RAM-based Low-Power Hybrid Register File for GPGPUs. In DAC, 2015.
  • [DAC] Xiaoxiao Liu*, Mengjie Mao*, Beiye Liu*, Boxun Li*, Hao Jiang, Yu Wang, Mark Barnell, Qing Wu, J. Joshua Yang, Hai Li, Yiran Chen, “Reno: A Highly-efficient Reconfigurable Neuromorphic Computing Accelerator Design”, in DAC 2015.
  • [HPCA] Xiaolong Xie*, Yun Liang, Yu Wang, Guangyu Sun, Tao Wang, “Coordinated Static and Dynamic Cache Bypassing for GPUs”, in HPCA 2015.
  • [DATE] Xiaoming Chen*, Yu Wang, Huazhong Yang, “A Fast Parallel Sparse Solver for SPICE-based Circuit Simulators”, in DATE 2015 (Long, acceptance rate 22%).
  • [DATE] Tianqi Tang*, Lixue Xia*, Boxun Li*, Rong Luo, Yu Wang, Yiran Chen, Huangzhong Yang, “Spiking Neural Network with RRAM : Can We Use it for Real-World Application?”, in DATE 2015 (Long, acceptance rate 22%) .
  • [FPGA] Xinyu Niu*, Wayne Luk and Yu Wang, "EURECA: On-Chip Configuration Generation for Effective Dynamic Data Access", FPGA 2015 (Long, acceptance rate 21%).
  • [ASPDAC] Wulong Liu*, Guoqing Chen, Yu Wang, Huazhong Yang, “Modeling and Optimization of Low Power Resonant Clock Mesh”, in ASPDAC 2015.
  • [ASPDAC] Peng Gu*, Boxun Li*, Tianqi Tang*, Shimeng Yu, Yu Cao, Yu Wang, Huazhong Yang, “Technological Exploration of RRAM Crossbar Array For Matrix-Vector Multiplication”, in ASPDAC? 2015.
  • [ASPDAC] Li-xue XIA*, Rong LUO, Bin ZHAO, Yu WANG, Hua-zhong YANG, “An Accurate and Low Cost PM2.5 Estimation Method Based on Artificial Neural Network”, in ASPDAC 2015.
• 2014
  • [FPT] Guohao Dai*, Yi Shan*, Fei Chen, Yu Zhang, Yu Wang, Kun Wang and Huazhong Yang, “Online Scheduling for FPGA Computation in the Cloud”, in International Conference on Field-Programmable Technology (FPT’14).
  • [FPT] Wenqiang Wang*, Kaiyuan Guo*, Mengyuan Gu*, Yuchun Ma and Yu Wang, “A Universal FPGA-based Floating-point Matrix Processor for Mobile Systems”, in International Conference on Field-Programmable Technology (FPT’14).
  • [ISIC] Tianqi Tang*, Rong Luo, Boxun Li*, Hai Li, Yu Wang, Huazhong Yang, “Energy Efficient Spiking Neural Network Design with RRAM Devices”, in ISIC 2014.
  • [CF] Fei Chen, Yi Shan*, Yu Zhang, Yu Wang, Hubertus Franke, Xiao Tao Chang and Kun Wang, "Enabling FPGAs in the Cloud", in Computer Frontiers (CF) 2014. [PDF download]
  • [DAC] Wulong Liu*, Guoqing Chen, Xue Han*, Yu Wang, Yuan Xie, Huazhong Yang, "Design Methodologies for 3D Mixed Signal Integrated Circuits: A Practical 12-bit SAR ADC Design Case", in DAC 2014.
  • [DAC] Xiaoming Chen*, Yu Wang, Yun Liang, Yuan Xie, Huazhong Yang, "Run-Time Technique for Simultaneous Aging and Power Optimization in GPGPUs", in DAC 2014.
  • [IJCNN] Boxun Li*, Erjin Zhou*, Bo Huang*, Jiayi Duan*, Yu Wang, Ningyi Xu, Jiaxing Zhang, Huazhong Yang, "Large Scale Recurrent Neural Network on GPU", in IJCNN 2014.
  • [DATE] Boxun Li*, Yu Wang, Yiran Chen, Helen Li, Huazhong Yang, "ICE: INline Calibration for Memristor Crossbar-based Computing Engine", in DATE 2014.
  • [DATE] Yu Wang, Boxun Li*, Rong Luo, Yiran Chen, Ningyi Xu, Huazhong Yang, "Energy Efficient Neural Networks for Big Data Analytics", in DATE 2014. (Invited Paper for Special Day on Advancing Electronics Beyond CMOS)
  • [ISQED] Song Yao*, Xiaoming Chen*, Yu Wang, Yuchun Ma, Yuan Xie, Huazhong Yang, "Efficient Region-Aware P/G TSV Planning for 3D ICs", in ISQED 2014.
  • [FPGA] Yuliang Sun*, Zilong Wang*, Sitao Huang*, Lanjun Wang, Yu Wang, Rong Luo, Huazhong Yang, "Accelerating Frequent Item Counting with FPGA", in FPGA 2014.
  • [ASPDAC] Miao Hu*, Yu Wang, Qinru Qiu, Yiran Chen, Hai Li, “The Stochastic Modeling of TiO2 Memristor and Its Usage in Neuromorphic System Design”, in ASPDAC 2014.
  • [ASPDAC] Xiaoming Chen*, Yu Wang, Yu Cao, Huazhong Yang, “Statistical Analysis of Random Telegraph Noise in Digital Circuits”, in ASPDAC 2014 (Best Paper Candidate).
  • [ASPDAC] Boxun Li*, Yuzhi Wang*, Yu Wang, Yiran Chen, Huazhong Yang, “Training Itself: Mixed-signal Training Acceleration for Memristor-based Neural Network”, in ASPDAC 2014.
• 2013
  • [ICFPT] Xinyu Niu*, José Gabriel F. Coutinho, Yu Wang and Wayne Luk, “Dynamic Stencil: Effective Exploitation of Run-time Resources in Reconfigurable Clusters”, in ICFPT 2013.
  • [ICFPT] Wen-Qiang Wang*, Jing Yan, Ning-Yi Xu, Yu Wang and Feng-Hsiung Hsu, “A Real-time High-quality Stereo Vision System on FPGA”, in ICFPT 2013.
  • [SC Workshop] Xiaoming Chen*, Du Su*, Yu Wang, Huazhong Yang, Nonzero Pattern Analysis and Memory Access Optimization in GPU-based Sparse LU Factorization for Circuit Simulation, SC'13 (Super Computing) workshop on Irregular Applications: Architectures & Algorithms
  • [HPCC] Sitao Huang*, Guohao Dai*, Yuliang Sun*, Zilong Wang*, Yu Wang and Huazhong Yang, “DTW-Based Subsequence Similarity Search on AMD Heterogeneous Computing Platform”, in HPCC 2013.
  • [ChinaCom] Xiang Chen, Ji Zhu*, Ziyu Wen*, Yu Wang, Huazhong Yang, "BER Guaranteed Optimization and Implementation of Parallel Turbo Decoding on GPU", in ChinaCom 2013.
  • [ICCAD] Y. Zhang*, I. Bayram, Y. Wang, H. Li and Y. Chen, “ADAMS: Asymmetric Differential STT-RAM Cell Structure for Reliable and High-performance Applications,” in ICCAD 2013.
  • [ISLPED] Boxun Li*, Yi Shan*, Miao Hu*, Yu Wang, Yiran Chen, Huazhong Yang, “Memristor Based Approximated Computation”, in ISLPED 2013.
  • [ISVLSI] Xin Li*, Wulong Liu*, Haixiao Du*, Yu Wang, Yuchun Ma, Huazhong Yang, "Whitespace-Aware TSV Arrangement in 3D Clock Tree Synthesis", to appear in ISVLSI 2013.
  • [DAC WIP] Wulong Liu*, Tao Zhang*, Xue Han*, Yu Wang, Yuan Xie, Huazhong Yang, "Design Methodologies for 3D Mixed Signal Integrated Circuits: a Practical 8-bit SAR ADC Design Case", in Work in Progress Session at DAC 2013.
  • [ISQED] Wulong Liu*, Haixiao Du*, Yu Wang, Yuchun Ma, Yuan Xie, Jinguo Quan, Huazhong Yang, "TSV aware Topology Generation for 3D Clock Tree Synthesis", in ISQED 2013.
  • [FPGA] Zilong Wang*, Sitao Huang*, Lanjun Wang, Hao Li, Yu Wang and Huazhong Yang, "Accelerating Subsequence Similarity Search Based on Dynamic Time Warping Distance with FPGA", in FPGA 2013. (long paper, acceptance rate 26%(long + short))
    
  • [ASPDAC] Shuai Tao*, Xiaoming Chen*, Yu Wang, Yuchun Ma, Yiyu Shi, Hui Wang, Huazhong Yang, "HS3DPG: Hierarchical Simulation for 3D P/G Network", in ASPDAC 2013. (acceptance rate 30%).
• 2012
  • [FPT] Yi Shan*, Zilong Wang*, Wenqiang Wang*, Yuchen Hao*, Yu Wang, Kuenhung Tsoi, Wayne Luk and Huazhong Yang, "FPGA based Memory Efficient High Resolution Stereo Vision System for Video Tolling", in ICFPT 2012.
  • [FPL] Brahim Betkaoui*, David Thomas, Yu Wang and Wayne Luk, "Parallel FPGA-based All Pairs Shortest Paths for sparse networks: A Human Brain Connectome Case study", in FPL 2012.
  • [ISVLSI] Hong Luo, Yu Wang, Yu Cao, Yuan Xie, Yuchun Ma and Huazhong Yang, "Temporal Performance Degradation under RTN: Evaluation and Mitigation for Nanoscale Circuits", in ISVLSI 2012. (Best Paper Award)
  • [DEBS] Zhaoran Wang*, Yu Zhang, Xiaotao Chang, Xiang Mi*, Yu Wang, Kun Wang and Huazhong Yang, "Pub/Sub on Stream: A Multi-Core Based Message Broker with QoS support" , in DEBS 2012 (22% acceptance rate).
  • [ASAP] Brahim Betkaoui*, Yu Wang, David B. Thomas, Wayne Luk, "A Reconfigurable Computing Approach for Efficient and Scalable Parallel Graph Exploration", in ASAP 2012.
  • [DAC] Ling Ren*, Xiaoming Chen*, Yu Wang, Chenxi Zhang*, Huazhong Yang, "Sparse LU Factorization for Parallel Circuit Simulation on GPU", in DAC 2012.
  • [DAC] W. Wen, Y. Zhang, Y. Chen, Y. Wang, and Y. Xie, “PS3-RAM: A Fast, Portable and Scalable Statistical STT-RAM Reliability Analysis Method,” in DAC 2012.
  • [HEART] (No Proceedings, poster) Yi Shan*, Zilong Wang*, Wenqiang Wang*, Yuchen Hao*, Yu Wang, Kuen Hung Tsoi, Wayne Luk, Huazhong Yang, "FPGA based Stereo Vision System for Future Video Tolling". In International Workshop on Highly-Efficient Accelerators and Reconfigurable Technologies, 2012. (Best Poster Award)
  • [IPDPSW] Mo Xu*, Xiaorui Zhang*, Yu Wang, ZiyuWen, Yi Xu, Ling Ren, Gaolang Gong, Ningyi Xu and HuazhongYang, "Probabilistic Brain Fiber Tractography on GPUs", in IPDPS Workshop: Hicomb 2012.
  • [IPDPSW] Xiaoming Chen, Yu Wang, Huazhong Yang, "Parallel Circuit Simulation on Multi/Many-core Systems", in IPDPS 2012 Phd Forum.
  • [ARC] Ruining He, Guoqiang Liang, Yuchun Ma, Yu Wang, Jinian Bian, "PDPR: Fine-Grained Placement for Dynamic Partially Reconfigurable FPGAs". in ARC 2012: 350-356.
  • [ASPDAC] Xiaoming Chen*, Yu Wang, Huazhong Yang, "An Adaptive LU Factorization Algorithm for Parallel Circuit Simulation", in ASPDAC 2012, pp. 359 - 364. (best paper nomination, 13 of 288)
  • [ASPDAC] Jing Xie*, Yu Wang, Yuan Xie, "Yield-Aware Time-Efficient Testing and Self-fixing Design for TSV-Based 3D ICs", in ASPDAC 2012, pp. 738-743.
  • [ASPDAC] Zuowei Li*, Yuchun Ma, Qiang Zhou, Yici Cai, Yu Wang, Tingting Huang, Yuan Xie, "Thermal-aware Power Network Design for IR Drop Reduction in 3D ICs", in ASPDAC 2012, pp. 47-52.
• 2011
  • [ICCAD] Yu WANG, Mo XU, Ling REN, Xiaorui ZHANG, Di WU, Yong HE, Ningyi XU, Huazhong YANG, "A Heterogeneous Accelerator Platform for Multi-Subject Voxel-based Brain Network Analysis", ICCAD'2011. pp.339~344.
  • [ISVLSI] Weichen Liu, Jiang Xu, Xuan Wang, Yu Wang, Wei Zhang, Yaoyao Ye, Xiaowen Wu, Mahdi Nikdast, Zhehui Wang. A Hardware-Software Collaborated Method for Soft-Error Tolerant MPSoC.? ISVLSI'2011. pp.260~265.
  • [MWSCAS] Hong Luo, Yu Wang, Jyothi Velamala, Yu Cao, Yuan Xie, and Huazhong Yang, "The impact of correlation between NBTI and TDDB on the performance of digital circuits", in IEEE MWSCAS 2011, pp 1-4.
    
  • [ARC] Wei Wu*, Yi Shan*, Xiaoming Chen*, Yu Wang, Huazhong Yang, "FPGA Accelerated Parallel Sparse Matrix Factorization for Circuit Simulations", in 7th International Symposium on Applied Reconfigurable Computing, pp 302-315.
  • [ISQED] Hong Luo, Xiaoming Chen*, Jyothi Velamala*, Yu Wang, Yu Cao, Vikas Chandra, Yuchun Ma and Huazhong Yang, "Circuit-level delay modeling considering both TDDB and NBTI", in ISQED'2011. pp.14~21.
  • [DATE] Tianji Wu*, Di Wu*, Yu Wang, Xiaorui Zhang*, Hong Luo, Ningyi Xu, Huazhong Yang, “Gemma in April: A Matrix-like Parallel Programming Architecture on OpenCL”, in Design, Automation and Test in Europe Conference and Exhibition (DATE) 2011, pp.703~708. [PDF]
  • [ASPDAC] Wulong Liu*, Yu Wang, Wei Liu, Yuchun Ma, Yuan Xie, Huazhong Yang, “On-Chip Hybrid Power Supply System for Wireless Sensor Nodes”, in ASPDAC 2011, pp 43-48.
  • [ASPDAC] Kan Wang, Yuchun Ma, Sheqin Dong, Yu Wang, Xianlong Hong, Jason Cong, "Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs", in ASPDAC 2011, pp 261-266.
  • [ASPDAC] Bei Yu, Sheqin Dong, Yuchun Ma, Tao Lin, Yu Wang, Song Chen, Satoshi Goto, "Network flow-based simultaneous retiming and slack budgeting for low power design", in ASPDAC 2011, pp. 473-478.
• 2010
  • [ICPADS] Di Wu*, Tianji Wu*, Yi Shan*, Yu Wang, Yong He, Ningyi Xu, Huazhong Yang, “Making Human Connectome Faster: GPU Acceleration of Brain Network Analysis”, to appear in Proceedings of the International Conference on Parallel and Distributed Systems - ICPADS 2010. [PDF]
  • [ICPP] Tianji Wu*, Bo Wang*, Yi Shan*, Feng Yan*, Yu Wang, Ningyi Xu, "Efficient PageRank and SpMV Computation on AMD GPUs", in Proceedings of the International Conference on Parallel Processing (ICPP) 2010, pp 81-89. [PDF]
  • [ASQED] (invited paper) Yu Wang, Yong He, Yi Shan*, Tianji Wu*, Di Wu* and Huazhong Yang, "Hardware Computing for Brain Network Analysis", in Asia Quality Electronic Design (ASQED) 2010, pp 219-222. [PDF]
  • [SASP]Yi Shan*, Tianji Wu*, Yu Wang, Bo Wang*, Zilong Wang*, Ningyi Xu, Huazhong Yang, "FPGA and GPU Implementation of Large Scale SpMV", in Proceedings of the 2010 IEEE 8th Symposium on Application Specific Processors, SASP'10, Anaheim, CA, United states, 2010, pp. 64 - 70. [PDF]
  • [ICGCS] Yao Wang*, Yu Wang, Jiang Xu, Huazhong Yang, "Performance Evaluation of On-Chip Sensor Network (SENoC) in MPSoC" , in International Conference on Green Circuits and Systems (ICGCS) 2010, pp 323-327. [PDF]
  • [ICGCS] Shuai Tao*, Yu Wang, Jiang Xu, Yuchun Ma, Yuan Xie, Huazhong Yang, "Simulation and Analysis of P/G Noise in TSV based 3D MPSoC", in International Conference on Green Circuits and Systems (ICGCS) 2010, pp 573-577. [PDF]
  • [FPGA] Yi Shan*, Bo Wang*, Jing Yan*, Yu Wang, Ningyi Xu, Huazhong Yang, "FPMR: MapReduce Framework on FPGA -- A Case Study of Rankboost Acceleration ", in ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA, Monterey, CA, United states, 2010, pp. 93 - 102.[PDF]
  • [FPGA] Jing Yan, Ningyi Xu, Xiongfei Cai, Rui Gao, Yu Wang, Rong Luo, Fenghsiung Hsu, "LambdaRank Acceleration for Relevance Ranking in Web Search Engines", in ISFPGA (abstract).
  • [ASPDAC]Yibo Chen*, Yuan Xie, Yu Wang, Andres Takach, “Parametric Yield Driven Resource Binding in Behavioral Synthesis with Multi-Vth/Vdd Library”, in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, Taipei, Taiwan, 2010, pp. 781 - 786.[PDF] (best paper candidate)
  • [ASPDAC] Yibo Chen*, Yuan Xie, Yu Wang, Andres Takach, “Minimizing Leakage Power in Aging-Bounded High-level Synthesis with Design Time Multi-Vth Assignment”, in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, Taipei, Taiwan, 2010, pp. 689-694.[PDF]
  • [ASPDAC] Paul Falkerstern*, Yuan Xie, Yao-wen Chang, Yu Wang, “Three Dimensional Integrated Circuit (3D IC) Floorplan and Power/Ground Network Co-synthesis”, in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, Taipei, Taiwan, 2010, pp. 169-174. [PDF]
  • [ASPDAC] Li Li*, Yuchun Ma, Ning Xu, Yu Wang, Xianlong Hong, “PS-FPG: Pattern Selection based co-design of Floorplan and Power/Ground Network with Wiring Resource Optimization”, in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, Taipei, Taiwan, 2010, pp. 769-774.[PDF]
  • [ASPDAC] Shenghua Liu*, Yuchun Ma, Xianlong Hong, Yu Wang, “Simultaneous Slack Budgeting and Retiming for Synchronous Circuits Optimization”, in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, Taipei, Taiwan, 2010, pp. 781 - 786.[PDF] (best paper candidate)
• 2009
  • [ICPADS] Bo Wang*, Tianji Wu*, Feng Yan*, Ruirui Li*, Ningyi Xu, Yu Wang, " RankBoost Acceleration on both NVIDIA CUDA and ATI Stream platforms ", in Proceedings of the International Conference on Parallel and Distributed Systems - ICPADS, Shenzhen, Guangdong, China, 2009, pp. 284 – 291.[PDF]
  • [TENCON] Guangming Yu*, Yu Wang, Huazhong Yang, Hui Wang, " A Fast-Locking All-Digital Phase-Locked Loop with a Novel Counter-Based Mode Switching Controller ", in IEEE Region 10 Annual International Conference, Proceedings/TENCON, Singapore, Singapore, 2009, pp 1-5. [PDF]
  • [CODES] Weichen Liu*, Zonghua Gu, Jiang Xu, Yu Wang, Mingxuan Yuan, "An Efficient Technique for Analysis of Minimal Buffer Requirements of Synchronous Dataflow Graphs with Model Checking", in Embedded Systems Week 2009 - 7th IEEE/ACM International Conference on Hardware/Software-Coesign and System Synthesis, CODES+ISSS 2009, Grenoble, France, 2009, pp. 61 - 69. [PDF](best paper candidate)
  • [CASES] Yu Wang, Jiang Xu, Shengxi Huang*, Weichen Liu*, Huazhong Yang, "A Case Study of On-Chip Sensor Network in Multiprocessor System-on-Chip", in Embedded Systems Week 2009 - 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES'09,Grenoble, France, 2009, pp. 241 - 249.[PDF]
  • [ASICON] Xiaowei Zhou*, Yu Wang, Huazhong Yang, "DCCB and SCC Based Fast Circuit Partition Algorithm For Parallel SPICE Simulation", in ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC, Changsha, China, 2009, pp. 1247 - 1250.[PDF]
  • [MTDT] Balaji Vaidyanathan*, Yu Wang, Yuan Xie, “Cost-Aware Lifetime Yield Analysis of Heterogeneous 3D On-Chip Cache”, in Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009, Hsinchu, Taiwan, 2009, pp. 65 - 70.[PDF]
  • [FPL] Jin Yan*, Ningyi Xu, Xiong-Fei Cai, Rui Gao, Yu Wang, Rong LUO, Feng-Hsiung Hsu, “FPGA-based Acceleration of Neural Network for Ranking Web Search Engine with a Streaming Architecture”, in FPL 09: 19th International Conference on Field Programmable Logic and Applications, Prague, Czech republic, 2009, pp. 662 - 665.[PDF]
  • [ISLPED] Xiaoming Chen, Yu Wang, Yu Cao, Yuchun Ma, Huazhong Yang, "Variation-Aware Supply Voltage Assignment for Minimizing Circuit Degradation and Leakage", 2009 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED'09, pp 39-44, 2009/8/19 [PDF] (best paper nomination, 7 of 72).
  • [ISVLSI] Yan Xu, Weichen Liu, Yu Wang, Jiang Xu, Xiaoming Chen, Huazhong Yang, “On-line MPSoC Scheduling Considering Power Gating Induced Power/Ground Noise”, 2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009, pp 109-114, 2009/5/14. [PDF]
  • [ISVLSI] Li Li, Yuchun Ma, Ning Xu, Yu Wang, Xianlong Hong, “Modern floorplanning with boundary clustering constraint”, 2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009, pp 79-84, 2009/5/14. [PDF]
  • [ISTD] Bo Zhao, Yu Wang, Huazhong Yang, Hui Wang, "The NBTI Impact on RF Front End in Wireless Sensor Networks", 2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09, 2009/4/28. [PDF]
  • [ISQED] Yu Wang, Xiaoming Chen, Wenping Wang, Varsha Balakrishnan, Yu Cao, Yuan Xie, and Huazhong Yang, "On the efficacy of Input Vector Control to mitigate NBTI effects and leakage power", 10th International Symposium on Quality Electronic Design, ISQED 2009, pp 19-26, 2009/3/16. [PDF]
  • [ISQED] Balaji Vaidyanathan, Anthony Oates, Yuan Xie, Yu Wang, "NBTI-Aware Statistical Circuit Delay Assessment", 10th International Symposium on Quality Electronic Design, ISQED 2009, pp 13-18, 2009/3/16. [PDF]
  • [DATE] Yu Wang, Xiaoming Chen, Wenping Wang, Yu Cao, Yuan Xie, Huazhong Yang, "Gate Replacement Techniques for Simultaneous Leakage and Aging Optimization", 2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09, pp 328-333, 2009/4/20. [PDF]
  • [ASPDAC] Michael DeBole, Ramakrishnan Krishnan, Varsha Balakrishnan, Wenping Wang, Luo Hong, Yu Wang, Yuan Xie , Yu Cao, N. Vijaykrishnan, " A Framework for Estimating NBTI Degradation of Microarchitectural Components", Asia and South Pacific Design Automation Conference 2009, ASP-DAC 2009, pp 455-460, 2009/1/19. [PDF]
• 2008
  • [APCCAS] Yu Wang, Kai Zhou, Zhonghai Lu, Huazhong Yang, "Dynamic TDM Virtual Circuit Implementation for NoCs", in APCCAS 2008, pp. 1533-1536. [PDF]
  • [ISQED] Qian Ding, Yu Wang, Hui Wang, Rong Luo, Huazhong Yang, " Output Remapping Technique for Soft-Error Rate Reduction in Critical Path, " in ISQED08, pp. 74-77 . [PDF]
  • [ASPDAC] Saihua Lin, Yu Wang, Rong Luo, Huazhong Yang, "A Capacitive Boosted Buffer Technique for High-Speed Process-Variation-Tolerant Interconnect in UDVS application ," in ASPDAC2008, pp. 304-309. [PDF]
• 2007
  • [ICCD] Ku He, Rong Luo, Yu Wang , “A Power Gating Scheme for Ground Bounce Reduction during Mode Transition,”in ICCD07, pp. 388-394. [PDF]
• [ASICON] Xukai Shen, Yu Wang , Rong Luo, Huazhong Yang, “Leakage power reduction through dual Vth assignment considering threshold voltage variation,” [pdf] in ASICON07, pp:1122 - 1125 .
• [PATMOS] Hong Luo, Yu Wang , Ku He, Rong Luo, Huazhong Yang, Yuan Xie, “A Novel Gate-level NBTI Delay Degradation Model with Stacking Effect,”[pdf] Proceedings of Power and Timing Modeling, Optimization and Simulation (PATMOS), Gothenburg, Sweden, September 3-5, 2007: 160-170, LNCS 4644.
• [ISQED] Hong Luo, Yu Wang , Ku He, Rong Luo, Huazhong Yang, Yuan Xie, “Modeling of PMOS NBTI Effect Considering Temperature variation,” [pdf] Proceedings of 8th International Symposium on Quality Electronic Design, 2007. ISQED '07, San Jose , USA , March 26-29, 2007: 139-144.
• [DATE] Yu Wang , Hong Luo, Ku He, Rong Luo, Huazhong Yang, Yuan Xie, “NBTI Modeling and Impact on the Input Vector Control Technique Considering Temperature Variation,”[pdf] Proceedings of Design Automation & Test in Europe Conference & Exhibition, 2007. DATE '07, Nice, France , April 16-20, 2007: 546-551.
• 2006
  • [APCCAS] Yongpan Liu, Yu Wang , Feng Zhang, Rong Luo, Hui Wang, "A New Thermal-Conscious System-Level Methodology for Energy-Efficient Processor Voltage Selection," in Procs of APCCAS 2006, pp:970-973. [PDF]
• [APCCAS] Yu Wang , Hui Wang, Huazhong Yang, "Fine-grain Sleep Transistor Placement Considering Leakage Feedback Gate," [pdf] in Procs of APCCAS 2006, pp:966-969.
• [ICNC] Yu Wang , Yongpan Liu, Rong Luo, Huazhong Yang, "Genetic Algorithm based Fine-grain Sleep Transistor Insertion Technique for Leakage Optimization," [pdf] in Advances in Natural Computation (ICNC 2006 Part I), LNCS 4221, pp 716-725.
• [PATMOS] Hai Lin, Yu Wang , Huazhong Yang, Rong Luo, Hui Wang, “IR-drop Reduction through Combinational Circuit Partitioning,”[pdf] in Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation (PATMOS 2006), LNCS 4148, pp. 370–381, 2006.
• [ISLPED] Yu Wang , Yongpan Liu, Rong Luo, Huazhong Yang, Hui Wang, "Two-phase Fine-grain Sleep Transistor Insertion Technique in Leakage Critical Circuits," [pdf] in Proc. of ISLPED06, pp:238-243.
• [ISQED] Yu Wang , Hai Lin, Huazhong Yang, Rong Luo, Hui Wang, “Simultaneous Fine-grain Sleep Transistor Placement and Sizing for Leakage Optimization,”[pdf] in Proc.of ISQED'06, San Jose, USA, March 2006, pp:723-728.
• 2005
  • [PRIME] Yu Wang , Huazhong Yang, Hui Wang, “Signal-path level Assignment for Dual-Vt Technique,” [pdf] in Proceedings of IEEE PRIME05, Volume 1, July 25, 2005 page(s):74 - 77

Workshops

• [NIPS workshop: Biglearn] Bo Wang, Yi Shan, Jing Yan, Yu Wang, Ningyi Xu, Huazhong Yang, "FPGA-based MapReduce Framework for Machine Learning", in Large-Scale Machine Learning: Parallelism and Massive Datasets in NIPS 2009: http://www.select.cs.cmu.edu/meetings/biglearn09.

Presentations

• ASQED'10, Penang, Malaysia, August, "Hardware Computing for Brain Network Analysis".
• Visiting NUS, SG, August, "Recent MPSoC research work in NICS Tsinghua".
• Visiting PSU, USA, April, "Recent MPSoC research work in NICS Tsinghua".
• ASPDAC'10, Taiwan, China, Jan, "Three Dimensional Integrated Circuit (3D IC) Floorplan and Power/Ground Network Co-synthesis".
• ISLPED'09, SF, USA, August, "Variation-Aware Supply Voltage Assignment for Minimizing Circuit Degradation and Leakage".
• DATE'09, Nice, France, April, "Gate Replacement Techniques for Simultaneous Leakage and Aging Optimization".
• APCCAS'08, Macao, China, Dec.,2008, "Dynamic TDM Virtual Circuit Implementation for NoCs".
• ASPDAC'08, Seoul, Korea, January, 2008, “A Capacitive Boosted Buffer Technique for High-Speed Process-Variation-Tolerant Interconnect in UDVS application”.
• ASICON'07, Guilin, China, October, 2007, “Leakage power reduction through dual Vth assignment considering threshold voltage variation”.
• DATE'07, Nice, France , April, 2007, “NBTI Modeling and Impact on the Input Vector Control Technique Considering Temperature Variation ”.
• APCCAS'06, Singapore , December, 2006, “Leakage Optimized DECAP Design for FPGAs”.
• APCCAS'06, Singapore , December, 2006, “Fine-grain Sleep Transistor Placement Considering Leakage Feedback Gate”.
• ISLPED'06, Munich , Germany , October, 2006, “ Two-phase Fine-grain Sleep Transistor Insertion Technique in Leakage Critical Circuits ”.
• PATMOS'06, Montpellier, France, September 2006, “IR-drop Reduction through Combinational Circuit Partitioning”.
• ISQED'06, San Jose , USA , March 2006, “ Simultaneous Fine-grain Sleep Transistor Placement and Sizing for Leakage Optimization”.

PhD Forum

• DATE 2007, “Circuit level Leakage Reduction Techniques in Deep Submicron Integrated Circuit Designs ” .
• IFIP VLSI-SOC 2007, "Leakage and NBTI Mitigation Techniques in Deep Submicron IC Designs ".

Book Chapter

• Rong Luo, Yu Wang, Yongpan Liu, “Digital Principles and Design,” (Chinese version), Tsinghua University Press.

Patent

• Huazhong Yang, Yu Wang, Rong Luo, Hui Wang, “A method to reduce power in DSM circuits”, China patent pending, Application No. 200410038009.8, Application Date: 2004.05.14.
• Huazhong Yang, Yu Wang, Rong Luo, Hui Wang, “A method to reduce Power/Ground current in DSM circuits”, China patent pending, Application No. 200410037661.8, Application Date: 2004.04.29.
• Huazhong Yang, Hong Luo, Yu Wang, Rong Luo, “A method to reduce the memory power in VLSI circuits,” China patent pending, Application No. CN200610057124.9.
• Rong Luo, Ku He, Yu Wang, Huazhong Yang, “A Power Gating Scheme for Ground Bounce Reduction during Mode Transition,” Applying for China patent.