Yu Wang's Homepage

Most of the papers are copyrighted by ACM or IEEE or Springer. They are posted here for your personal use, to ensure timely dissemination of research work with no commercial purpose

DBLP Link: 汪玉, EE Dept. Tsinghua University, Beijing, China

Journal Publications

• [IEEE TDSC] Yu Wang, Hong Luo, Ku He, Rong Luo, Huazhong Yang, Yuan Xie, "Temperature-Aware NBTI Modeling and the Impact of Standby Leakage Reduction Techniques on Circuit Performance Degradation", to appear in IEEE Trans on Dependable and Security Computing.
• [IEEE TVLSI] Yu Wang , Ku He, Rong Luo, Hui Wang, Huazhong Yang, “Two-phase Fine-grain Sleep Transistor Insertion Technique in Leakage Critical Circuits,” in IEEE Transaction on VLSI, Volume 16, Issue 9, Sept. 2008 Page(s):1101 - 1113.
• [IEEE TVLSI] Yu Wang, Xiaoming Chen, Wenping Wang, Yu Cao, Yuan Xie, Huazhong Yang, "Leakage Power and Circuit Aging Co-Optimization by Gate Replacement Techniques", to appear in TVLSI.
• [CJE] Yu Wang , Hong Luo, Ku He, Rong Luo, Huazhong Yang, Yuan Xie, “NBTI-aware Dual Vth Assignment for Leakage Reduction and Lifetime Assurance,” in Chinese Journal of Electronics, Issue 2, Feb. 2009, pp: 225-230.
• [CJS] Huazhong Yang, Yu Wang , Hai Lin, Rong Luo, Hui Wang, “Fine-grain Sleep Transistor Insertion for Leakage Reduction,” in Chinese Journal of Semiconductors, 2006, Vol.27, No.2, pp:258-265.
• [JCSC] Yu Wang ,Huazhong Yang, Hui Wang, “Signal-path Level Dual-Vt Assignment for Leakage Power Reduction,” [pdf] in Journal of Circuits, System and Computers, 2006, Vol. 15, No. 2, pp:179-216.
• [JCSC] Yu Wang, Xukai Shen, Rong Luo, Huazhong Yang, Leakage power reduction through Dual Vth assignment considering threshold voltage variation, in Journal of Circuits, Systems and Computers, 18(7), pp 1243-1261, 2009/11.
• [IEICE] Hong Luo, Yu Wang, Rong Luo, Huazhong Yang and Yuan Xie," Temperature-aware NBTI Modeling Techniques in Digital Circuits ", in IEICE Trans. on Electronics, E92C(6), pp 875-886, 2009/6.
• [IEICE] Yuchun Ma, Xin Li, Yu Wang, Xianlong Hong, "Thermal- Aware Incremental Floorplanning for 3D ICs  based on MILP Formulation", to appear in IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences.
• [JEC] Hong Luo, Yu Wang, Rong Luo, Huazhong Yang, "Software Tools for Analyzing NBTI-induced Digital Circuit Degradation," in Journal of Electronics (China), Volume 26, Number 5, 2009.09, pp.715-719. .
• [JEST] Bo Zhao, Yu Wang, Huazhong Yang, and Hui Wang, "The NBTI Impact on RF Front End in Wireless Sensor Networks", to appear in Journal of Electronic Science and Technology.
• [IJE] Qian Ding, Yu Wang, Hui Wang, Rong Luo, Huazhong Yang, SERSim: a Soft Error Rate Simulator and a Case Study for a 32-bit OpenRisc 1200 Microprocessor, to appear in International Journal of Electronics.
• [IET CDT] Qian Ding, Yu Wang , Hui Wang, Rong Luo, Huazhong Yang, Output Remapping Technique for Critical Paths Soft-Error Rate Reduction, to appear in IET Computers & Digital Techniques.
• [IET CDS] Guangming Yu, Yu Wang, Huazhong Yang, Hui Wang, "Fast-Locking All-Digital Phase-Locked Loop with Digitally Controlled Oscillator Tuning Word Estimating and Presetting", to appear in IET CDS.
• [Springer IJPP] Michael DeBole, Ramakrishnan Krishnan, Varsha Balakrishnan, Wenping Wang, Luo Hong, Yu Wang, Yuan Xie , Yu Cao, N. Vijaykrishnan, " NewAge: A Framework for Estimating NBTI Degradation of Microarchitectural Components",? in International Journal of Parallel Programming, Volume 37, Number 4, 2009.08, pp 417-431.
• [submitted to JS] Qian Ding, Yu Wang , Hui Wang, Rong Luo, Huazhong Yang, Soft Error Generation Analysis in Combinational Logic Circuits, submitted to Journal of Semiconductors.
• [submitted to TVLSI] Yu Wang, Jiang Xu, Yan Xu, Weichen Liu, Huazhong Yang, " Power Gating Aware Task Scheduling in MPSoC", submitted to TVLSI (major revision).

Conference Publications

• 2010
  • [FPGA] Yi Shan, Bo Wang, Jing Yan, Yu Wang, Ningyi Xu, Huazhong Yang, "FPMR: MapReduce Framework on FPGA -- A Case Study of Rankboost Acceleration ", to appear in ISFPGA.
  • [FPGA] Jing Yan, Ningyi Xu, Xiongfei Cai, Rui Gao, Yu Wang, Rong Luo, Fenghsiung Hsu, "LambdaRank Acceleration for Relevance Ranking in Web Search Engines", to appear in ISFPGA.
  • [ASPDAC] Yibo Chen, Yu Wang, Yuan Xie, Andres Takach, “Parametric Yield Driven Resource Binding in Behavioral Synthesis with Multi-Vth/Vdd Library”, in ASPDAC 2010. (best paper candidate)
  • [ASPDAC] Yibo Chen, Yu Wang, Yuan Xie, Andres Takach, “Minimizing Leakage Power in Aging-Bounded High-level Synthesis with Design Time Multi-Vth Assignment”, in ASPDAC 2010.
  • [ASPDAC] Paul Falkerstern, Yuan Xie, Yao-wen Chang, Yu Wang, “Three Dimensional Integrated Circuit (3D IC) Floorplan and Power/Ground Network Co-synthesis”, to appear in ASPDAC 2010.
  • [ASPDAC] Li Li, Yuchun Ma, Ning Xu, Yu Wang, Xianlong Hong, “PS-FPG: Pattern Selection based co-design of Floorplan and Power/Ground Network with Wiring Resource Optimization”, in ASPDAC 2010.
  • [ASPDAC] Shenghua Liu, Yuchun Ma, Xianlong Hong, Yu Wang, “Simultaneous Slack Budgeting and Retiming for Synchronous Circuits Optimization”, in ASPDAC 2010.(best paper candidate)
• 2009
  • [ICPADS] Bo Wang, Tianji Wu, Feng Yan, Ruirui Li, Ningyi Xu, Yu Wang, "RankBoost Acceleration on both NVIDIA CUDA and ATI Stream platforms ", in International Conference on Parallel and Distributed Systems (ICPADS'09).
  • [TENCON] Guangming Yu, Yu Wang, Huazhong Yang, Hui Wang, "A Fast-Locking All-Digital Phase-Locked Loop with a Novel Counter-Based Mode Switching Controller ", in TENCON 2009.
  • [CODES] Weichen Liu, Zonghua Gu, Jiang Xu, Yu Wang, Mingxuan Yuan, "An Efficient Technique for Analysis of Minimal Buffer Requirements of Synchronous Dataflow Graphs with Model Checking", in CODES 2009. (best paper candidate)
  • [CASES] Yu Wang, Jiang Xu, Shengxi Huang, Weichen Liu, Huazhong Yang, "A Case Study of On-Chip Sensor Network in Multiprocessor System-on-Chip", in CASES 2009.
  • [ASICON] Xiaowei Zhou, Yu Wang, Huazhong Yang, "DCCB and SCC Based Fast Circuit Partition Algorithm For Parallel SPICE Simulation", in ASICON 2009.
  • [MTDT] Balaji Vaidyanathan, Yu Wang, Yuan Xie, “Cost-Aware Lifetime Yield Analysis of Heterogeneous 3D On-Chip Cache”, in MTDT 2009.
  • [FPL] Jing Yan, Ningyi Xu, Xiongfei Cai, Rui Gao, Yu Wang, Rong Luo, Fenghsiung Hsu, "FPGA based Acceleration of Neural Network for Ranking in Web Search Engine with a Streaming Architecture", FPL 09: 19th International Conference on Field Programmable Logic and Applications, pp 662-665, 2009/8/31.
  • [ISLPED] Xiaoming Chen, Yu Wang, Yu Cao, Yuchun Ma, Huazhong Yang, "Variation-Aware Supply Voltage Assignment for Minimizing Circuit Degradation and Leakage", 2009 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED'09, pp 39-44, 2009/8/19 (best paper nomination, 7 of 72).
  • [ISVLSI] Yan Xu, Weichen Liu, Yu Wang, Jiang Xu, Xiaoming Chen, Huazhong Yang, “On-line MPSoC Scheduling Considering Power Gating Induced Power/Ground Noise”, 2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009, pp 109-114, 2009/5/14.
  • [ISVLSI] Li Li, Yuchun Ma, Ning Xu, Yu Wang, Xianlong Hong, “Modern floorplanning with boundary clustering constraint”, 2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009, pp 79-84, 2009/5/14.
  • [ISTD] Bo Zhao, Yu Wang, Huazhong Yang, Hui Wang, "The NBTI Impact on RF Front End in Wireless Sensor Networks", 2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09, 2009/4/28.
  • [ISQED] Yu Wang, Xiaoming Chen, Wenping Wang, Varsha Balakrishnan, Yu Cao, Yuan Xie, and Huazhong Yang, "On the efficacy of Input Vector Control to mitigate NBTI effects and leakage power", 10th International Symposium on Quality Electronic Design, ISQED 2009, pp 19-26, 2009/3/16.
  • [ISQED] Balaji Vaidyanathan, Anthony Oates, Yuan Xie, Yu Wang, "NBTI-Aware Statistical Circuit Delay Assessment", 10th International Symposium on Quality Electronic Design, ISQED 2009, pp 13-18, 2009/3/16.
  • [DATE] Yu Wang, Xiaoming Chen, Wenping Wang, Yu Cao, Yuan Xie, Huazhong Yang, "Gate Replacement Techniques for Simultaneous Leakage and Aging Optimization", 2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09, pp 328-333, 2009/4/20.
  • [ASPDAC] Michael DeBole, Ramakrishnan Krishnan, Varsha Balakrishnan, Wenping Wang, Luo Hong, Yu Wang, Yuan Xie , Yu Cao, N. Vijaykrishnan, " A Framework for Estimating NBTI Degradation of Microarchitectural Components", Asia and South Pacific Design Automation Conference 2009, ASP-DAC 2009, pp 455-460, 2009/1/19.
• 2008
  • [APCCAS] Yu Wang, Kai Zhou, Zhonghai Lu, Huazhong Yang, "Dynamic TDM Virtual Circuit Implementation for NoCs", in APCCAS 2008, pp. 1533-1536.
  • [ISQED] Qian Ding, Yu Wang, Hui Wang, Rong Luo, Huazhong Yang, " Output Remapping Technique for Soft-Error Rate Reduction in Critical Path, " in ISQED08, pp. 74-77 .
  • [ASPDAC] Saihua Lin, Yu Wang, Rong Luo, Huazhong Yang, "A Capacitive Boosted Buffer Technique for High-Speed Process-Variation-Tolerant Interconnect in UDVS application ," in ASPDAC2008, pp. 304-309.
• 2007
  • [ICCD] Ku He, Rong Luo, Yu Wang , “A Power Gating Scheme for Ground Bounce Reduction during Mode Transition,”in ICCD07, pp. 388-394.
• [ASICON] Xukai Shen, Yu Wang , Rong Luo, Huazhong Yang, “Leakage power reduction through dual Vth assignment considering threshold voltage variation,” [pdf] in ASICON07, pp:1122 - 1125 .
• [PATMOS] Hong Luo, Yu Wang , Ku He, Rong Luo, Huazhong Yang, Yuan Xie, “A Novel Gate-level NBTI Delay Degradation Model with Stacking Effect,”[pdf] Proceedings of Power and Timing Modeling, Optimization and Simulation (PATMOS), Gothenburg, Sweden, September 3-5, 2007: 160-170, LNCS 4644.
• [ISQED] Hong Luo, Yu Wang , Ku He, Rong Luo, Huazhong Yang, Yuan Xie, “Modeling of PMOS NBTI Effect Considering Temperature variation,” [pdf] Proceedings of 8th International Symposium on Quality Electronic Design, 2007. ISQED '07, San Jose , USA , March 26-29, 2007: 139-144.
• [DATE] Yu Wang , Hong Luo, Ku He, Rong Luo, Huazhong Yang, Yuan Xie, “NBTI Modeling and Impact on the Input Vector Control Technique Considering Temperature Variation,”[pdf] Proceedings of Design Automation & Test in Europe Conference & Exhibition, 2007. DATE '07, Nice, France , April 16-20, 2007: 546-551.
• 2006
  • [APCCAS] Yongpan Liu, Yu Wang , Feng Zhang, Rong Luo, Hui Wang, "A New Thermal-Conscious System-Level Methodology for Energy-Efficient Processor Voltage Selection," in Procs of APCCAS 2006, pp:970-973.
• [APCCAS] Yu Wang , Hui Wang, Huazhong Yang, "Fine-grain Sleep Transistor Placement Considering Leakage Feedback Gate," [pdf] in Procs of APCCAS 2006, pp:966-969.
• [ICNC] Yu Wang , Yongpan Liu, Rong Luo, Huazhong Yang, "Genetic Algorithm based Fine-grain Sleep Transistor Insertion Technique for Leakage Optimization," [pdf] in Advances in Natural Computation (ICNC 2006 Part I), LNCS 4221, pp 716-725.
• [PATMOS] Hai Lin, Yu Wang , Huazhong Yang, Rong Luo, Hui Wang, “IR-drop Reduction through Combinational Circuit Partitioning,”[pdf] in Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation (PATMOS 2006), LNCS 4148, pp. 370–381, 2006.
• [ISLPED] Yu Wang , Yongpan Liu, Rong Luo, Huazhong Yang, Hui Wang, "Two-phase Fine-grain Sleep Transistor Insertion Technique in Leakage Critical Circuits," [pdf] in Proc. of ISLPED06, pp:238-243.
• [ISQED] Yu Wang , Hai Lin, Huazhong Yang, Rong Luo, Hui Wang, “Simultaneous Fine-grain Sleep Transistor Placement and Sizing for Leakage Optimization,”[pdf] in Proc.of ISQED'06, San Jose, USA, March 2006, pp:723-728.
• 2005
  • [PRIME] Yu Wang , Huazhong Yang, Hui Wang, “Signal-path level Assignment for Dual-Vt Technique,” [pdf] in Proceedings of IEEE PRIME05, Volume 1, July 25, 2005 page(s):74 - 77

Workshops

• [NIPS workshop: Biglearn] Bo Wang, Yi Shan, Jing Yan, Yu Wang, Ningyi Xu, Huazhong Yang, "FPGA-based MapReduce Framework for Machine Learning", to appear in Large-Scale Machine Learning: Parallelism and Massive Datasets in NIPS 2009: http://www.select.cs.cmu.edu/meetings/biglearn09.

Presentations

• ISLPED'09, SF, USA, August, "Variation-Aware Supply Voltage Assignment for Minimizing Circuit Degradation and Leakage".
• DATE'09, Nice, France, April, "Gate Replacement Techniques for Simultaneous Leakage and Aging Optimization".
• APCCAS'08, Macao, China, Dec.,2008, "Dynamic TDM Virtual Circuit Implementation for NoCs".
• ASPDAC'08, Seoul, Korea, January, 2008, “A Capacitive Boosted Buffer Technique for High-Speed Process-Variation-Tolerant Interconnect in UDVS application”.
• ASICON'07, Guilin, China, October, 2007, “Leakage power reduction through dual Vth assignment considering threshold voltage variation”.
• DATE'07, Nice, France , April, 2007, “NBTI Modeling and Impact on the Input Vector Control Technique Considering Temperature Variation ”.
• APCCAS'06, Singapore , December, 2006, “Leakage Optimized DECAP Design for FPGAs”.
• APCCAS'06, Singapore , December, 2006, “Fine-grain Sleep Transistor Placement Considering Leakage Feedback Gate”.
• ISLPED'06, Munich , Germany , October, 2006, “ Two-phase Fine-grain Sleep Transistor Insertion Technique in Leakage Critical Circuits ”.
• PATMOS'06, Montpellier, France, September 2006, “IR-drop Reduction through Combinational Circuit Partitioning”.
• ISQED'06, San Jose , USA , March 2006, “ Simultaneous Fine-grain Sleep Transistor Placement and Sizing for Leakage Optimization”.

PhD Forum

• DATE 2007, “Circuit level Leakage Reduction Techniques in Deep Submicron Integrated Circuit Designs ” .
• IFIP VLSI-SOC 2007, "Leakage and NBTI Mitigation Techniques in Deep Submicron IC Designs ".

Book Chapter

• Rong Luo, Yu Wang, Yongpan Liu, “Digital Principles and Design,” (Chinese version), Tsinghua University Press.

Patent

• Huazhong Yang, Yu Wang, Rong Luo, Hui Wang, “A method to reduce power in DSM circuits”, China patent pending, Application No. 200410038009.8, Application Date: 2004.05.14.
• Huazhong Yang, Yu Wang, Rong Luo, Hui Wang, “A method to reduce Power/Ground current in DSM circuits”, China patent pending, Application No. 200410037661.8, Application Date: 2004.04.29.
• Huazhong Yang, Hong Luo, Yu Wang, Rong Luo, “A method to reduce the memory power in VLSI circuits,” China patent pending, Application No. CN200610057124.9.
• Rong Luo, Ku He, Yu Wang, Huazhong Yang, “A Power Gating Scheme for Ground Bounce Reduction during Mode Transition,” Applying for China patent.