Yu Wang's Homepage

Research on Low Power Design methodology

• Leakage Power Reduction
  • Leakage Power is becoming increasingly important with technology scaling.
• Key Technologies
  • Dual Vth Assignment
  • Power Gating
  • Input Vector Control

Reliability Evaluator (Circuit level to System level)

• Background and Aim
  • NBTI and Soft Error have become two of the most critical reliability issues in today's UVLSI design. Currently we are building up a reliablity evaluator from circuit level to the system level to help the designers in the design phase. Our aim is to evaluate the system's reliability quickly and precisely.
• Tasks
  • Circuit level Modeling based on PTM model
  • Circuit level Evaluator
  • System level Modeling and Evaluator
  • Reliability aware design methodolgies
• Reliability mechanisms
  • Negative Bias Tempreature Instability
  • Soft Error
  • Power Ground Noise

General FPGA-based Acceleration for Machine Learning (MSRA)

• Background
  • Machine learning applications are currently becoming more and more important in various fields, such as web search and business intelligence. The real world machine learning applications usually have large scale data sets and require huge computation resources. The acceleration of machine learning algorithms thus attracts the interests of researchers from both the industry and the academia.
  • FPGA-based accelerator, as the alternative to other acceleration methods (including multi-core CPU, GPU, and distributed system), could provide fine-grained parallelism and good locality with a certain scale of data. On the other side, the FPGA-based accelerator has limitations in the scalability (scaling from single PC to cluster of servers, or even to data centers) and the reliability (recovering from communication or computer failures) on large scale data sets (Tera or Peta level). Current work mainly focuses on point solution that has unique hardware architecture (or circuit structure) for a specific algorithm. To successfully design such an accelerator requires efforts of hardware/software/algorithm guys, and the result is hard to be re-used for other similar projects.
• Aims and Tasks
  • We are trying to find a solution to accelerate most of machine learning algorithms as an application domain, in order to provide
    • (1) Efficient hardware architecture,
    • (2) Interfaces to OS

Research on FPGA based Anti-Degradation Machine Learning (NSFC)

• Project Description
  • The hardware platform is becoming one of the main driving forces of machine learning. Meanwhile, reliability problems, such as aging effect and soft errors, in the hardware platforms of machine learning will become hot research topics. In this project, FPGA-based anti-aging machine learning will be studied. First of all, we will try to explore the parallelism in machine learning algorithms and analyze the reliability/performance in different levels; secondly, after building an anti-aging FPGA function units and connections library, we will try to find a methodology to implement reliable machine learning on FPGA efficiently; thirdly, we will dynamically reconfigure FPGA based on the run time information to ensure the lifetime requirement of machine learning; at last we will try to explore if there exist a new architecture for anti-aging machine learning. We hope through this project, we will be able to effectively solve some performance, reliability, and design complexity problems in machine learning application domain.

Multi-Metric Incremental Floorplanning for SOC (TNLIST)

• Multi-Metric: High Performance, High reliability, and low power

SRT program

• FPGA based Machine Learning Algorithm Implementation
• Communication Strategy of MPSoC
• GPU based Machine Learning Algorithm Implementation